Conventionally popular digital systems consist of synchronous systems that use clock signals. That is, data read and write timings are controlled by externally providing a storage element such as a register with a clock signal of a specified cycle. Since such a synchronous digital system uses a clock to hide a transient phenomenon associated with changes in signal, logic design is simple and can be automated easily.
However, the synchronous digital system, which distributes a clock throughout the system, has various problems as described below.
First, in the synchronous digital system, a clock skew problem must be considered. The clock skew is the absolute value of the difference between the time required by a clock to reach one element and the time required by the clock to reach another element. If the value of the clock skew is large, data is not transferred correctly, thereby causing malfunction. If, for example, a clock for a source latch arrives faster than a clock for a destination latch, output data from the source latch is changed before the data is loaded into the destination latch, resulting in malfunction. On the contrary, if the clock for the destination latch arrives faster than the clock for the source latch, the destination latch takes output data from the source latch before the data has been updated, so the destination latch takes the same data twice, resulting in malfunction. Thus, to prevent timing faults, a sufficiently long clock cycle must be used for the synchronous digital system considering the time for data signals to propagate through elements, the time for data signals to reach elements in the next stage, and setup time.
Second, even if the processing speed of elements is increased, the synchronous digital system cannot obtain the benefits of the fast processing. Due to the recent significant improvement of semiconductor and integrated circuit techniques, the processing speed of elements has been improved, while the scale of the overall system has been increased. Consequently, instead of element delay, which is a conventional problem, wiring delay is becoming a dominant factor in design. The synchronous digital system using a clock cannot reduce the wiring delay easily, so even if faster elements are developed in the future, it will be difficult to improve system performance using these elements.
Third, the synchronous digital system cannot reduce power consumption easily because a clock is distributed throughout the system to instantaneously and simultaneously change the system. Thus, it is difficult to sufficiently meet the demand in the market for the reduction of power consumption in various portable digital systems, such as portable information terminals and cellular telephones.
Fourth, the synchronous digital system is relatively easily affected by a change in environment such as power supply voltage or ambient temperature. That is, if the processing speed of elements is varied due to a change in environment such as voltage or temperature, the timing with the clock may become incorrect, may possibly result in malfunction. As a result, the synchronous digital system requires environment management costs for a voltage control circuit and a CPU cooler.
On the other hand, asynchronous digital systems, which do not use a clock, are also known. In 1940s, when computers were first developed, asynchronous processors using vacuum tubes and relays were developed. Asynchronous digital systems are event-driven and finish the current processing before executing the subsequent processing.
Thus, due to the capability of executing subsequent processing without waiting for arrival of a clock signal, the asynchronous digital system can obtain the benefits of faster elements. In addition, in the asynchronous digital system, since a signal transition only occurs at a required time in a required place, power consumption can be significantly reduced using CMOS LSIs that require little power consumption if there is no signal transition. Furthermore, due to the unlikeliness to be affected by unpredictable delay variations, the asynchronous digital system can tolerate changes in environment, reduce environment management costs, and obtain stable operations under ultimate conditions, for example, in space or an abyss.
If a signal transition occurs out of a specified timing range, that is, if a timing fault occurs, the circuit may possibly malfunction. Thus, in designing a digital system, whether synchronous or asynchronous, reasonable assumptions must be made on the delay in elements or wiring and a correctly operating circuit must be designed based on these assumptions by considering device technologies, logic design methods, layout methods, packaging methods, and system operation environment used.
If a pessimistic delay assumption is made on possible delay variations, the constraints on the delay will be reduced during technology mapping or layout, while the amount of circuits is increased and the speed is reduced. Conversely, if an optimistic delay assumption is used, strict constraints must be followed during technology mapping or layout. Of course, if the nature of the device used is not compatible with the delay assumption, then reliability, the amount of circuits, and the easiness of design are all affected.
The most pessimistic delay assumption is a delay insensitive (DI) model assuming that wiring and element delays are finite but that their upper limits are unknown. In the DI model, however, it is known that the use of only branching and a single-output element cannot constitute a practical circuit.
An arbitrary practical circuit can be configured by adding to the DI model the assumption that the difference in the time for a signal to reach each branched portion can be neglected if the wiring is branched. This is called the quasi-delay insensitive (QDI) model.
The asynchronous digital system is described in detail in, for example, (1) T. Nanya, "Asynchronous Processors--Toward High-performance VLSI Systems," Information Processing, vol 134, no.1, pp. 72-80, January, 1993, (2) S. B. Furber, P. Day, J. D. Garside, N. C. Paver, and J. V. Woods, "AMULTEL1: A micropipelined ARM," in Proc. IEEE Computer Conf., pp. 476-485, March 1994, (3) T. Nanya, Y. Ueno, H. Kagotani, M. Kuwako, and A. Takamura, "TITAC: Design of quasi-delay-insensitive microprocessor," IEEE Design & Test of Computers, vol.11, no.2, pp.50-63, 1994, (4) Y. Ueno, A. Takamura, K. Ozawa, H. Kagotani, M. Kuwako, and T. Nanya, "Design and Evaluation of Asynchronous Processor TITAC" IEICE Technical Report, FIS94-26, April 1994, (5) Y. Ueno, A. Takamura, and T. Nanya, "Delay Insensitivity of Asynchronous Processor TITAC," 1995 IEICE National Meeting 1, no. D-140, March 1995.
The conventional asynchronous digital system described above uses the DI or the QDI model as a delay assumption for the overall system. If elements with a very large fanout or wires extending over a chip from edge to edge are required, it is appropriate to assume that the upper limit of the delay in such elements or wires is unknown.
The system, however, has a very small number of elements with a very large fanout or wires extending over a chip from edge to edge. For most of the remaining elements or wires, it can be assumed that the extent of delay variations can be predicted by imposing appropriate constraints during technology mapping or layout.
That is, since the conventional technique that uniformly applies the QDI model to the overall system always confirms the completion of the current processing before executing the subsequent processing, the system can operate stably to achieve high reliability even if actual delay is substantially varied by a change in temperature or the like. The asynchronous digital system according to the conventional technique, however, requires the time to confirm the completion of processing, so the processing speed may be reduced compared to the synchronous digital system.